1. Field of the Invention
The present invention provides a boundary scan connector test method, and more particularly, to a boundary scan connector test method capable of fully utilizing test I/O modules.
2. Description of the Prior Art
After forming a printed circuit board, the printed circuited board has to be installed with a few integrated circuits to form a useful printed circuit board assembly (PCBA). And to ensure normal operations of the PCBA, the integrated circuits will be made with built-in boundary scan circuits, and pins for boundary scan so as to test if the integrated circuits on the PCBA can perform normally.
Please refer to FIG. 1. FIG. 1 is a perspective view of a PCBA 10 and a test input/output (I/O) module 12 according to the prior art. The PCBA 10 comprises two integrated circuits 14, 16 and three connectors 18, 20, 21. The test I/O module 12 comprises an integrated circuit 22 which can be a field programmable gate array (FPGA) or an erasable programmable logic device (EPLD).
In the prior art, a user has to determine and select connectors, or pins of connectors which may be relevant to boundary scan. If the user determines that on the PCBA 10, pins 24, 26, 28 of the integrated circuit 14 and pins 30, 32, 34, 36 of the integrated circuit 16 may be relevant to boundary scan, then the user will determine that the connector 18 is relevant to boundary scan, and the connectors 20, 21 are irrelevant to boundary scan. Or the user will determine that pins 38, 42, 46 of the connector 18 are relevant to boundary scan, and other pins of the connectors 18, 20, 21 are irrelevant to boundary scan. The description file of the PCBA 10 will correspond the pin 38 of the connector 18 to the pin 40 of the test I/O module 12, the pin 42 of the connector 18 to the pin 44 of the test I/O module 12, the pin 46 of the connector 18 to the pin 48 of the test I/O module 12. Then the description file of the PCBA 10 and the description file of the test I/O module 12 will be accessed together. And the mode of the PCBA 10 and test I/O module 12 will be set as the boundary scan mode to determine which pins on the PCBA 10 and test I/O module 12 are relevant to boundary scan. If the wiring report generated by executing an auto test program generator shows that the pins 24, 28 of the integrated circuit 14 and the pins 30, 34 of the integrated circuit 16 are used to perform boundary scan, and the pin 26 of the integrated circuit 14 and the pins 32, 36 of the integrated circuit 16 are not used to perform boundary scan, then the user will electrically connect the pin 38 of the connector 18 to the pin 40 of the integrated circuit 22, and the pin 46 of the connector 18 to the pin 48 of the integrated circuit 22, but will not electrically connect the pin 42 of the connector 18 to the pin 44 of the integrated circuit 22. Then digital signals can be input to the PCBA 10 through the test I/O module 12 to check if the PCBA 10 can function normally.
Please refer to FIG. 2. FIG. 2 is a flowchart of a prior art boundary scan connector test method 200. The method 200 comprises the following steps:
Step 210: a user determines and selects the connector 18 which may be relevant to boundary scan, or the pins 38, 42, 46 of the connector 18 which may be relevant to boundary scan;
Step 220: read the description file of the PCBA 10 and the description file of the test I/O module 12;
Step 230: set the boundary scan integrated circuit of the PCBA 10 to determine pins related to boundary scan on the PCBA 10;
Step 240: execute the auto test program generator to generate a wiring report;
Step 250: a user electrically connects the pins 40, 48 on the test I/O module 12 to the pins 38, 46 of the connector 18 on the PCBA 10 according to the wiring report;
Step 260: input digital signals to the PCBA 10 through the test I/O module 12 to check if the PCBA 10 can function normally.
In step 210, to ensure all pins which may be relevant to boundary scan are selected, instead of selecting pins which may be relevant to boundary scan, a user usually selects all connectors which include pins possibly relevant to boundary scan. Thus in FIG. 1, instead of selecting possible pins on the connector 18, a user may select the connector 18. When selecting the connector 18 instead of possible pins on the connector 18, all pins of the connector 18 are selected. At the very least, to ensure all pins possibly relevant to boundary scan are selected, the number of pins on the connector 18 selected by the user will exceed the number of pins actually relevant to boundary scan. However in step 220, the pins 38, 42, 46 of the connector 18 selected by the user is linked to the pins of the integrated circuit on the test I/O module 12 one by one, thus each of the selected pins 38, 42, 46 will correspond to one of the pins 40, 44, 48. When step 230 finds the pins 38, 46 of the connector 18 are related to boundary scan but the pin 42 is not, the pin 42 which is not related to boundary scan but was falsely selected as related to boundary scan will be included in the wiring report generated by step 240. And the wiring report will report that the pin 42 and pin 44 should not be electrically connected with any pin. Because the pin 44 is not to be electrically connected with any pin, the pin 44 is left idle and is wasted. In a worse case, if the user selected the connector 18 instead of selecting the pins 38, 42, 46 of the connector 18 in step 210, then all of the pins of the connector 18 would be determined as might be relevant to boundary scan. Then in the wiring report, a great number of pins of the connector 18 and a great number of pins on the test I/O module 12 will be reported as not needing electrical connections, causing a severe waste of test I/O module 12 resource.